The DECT ciphering algorithm, like most data ciphering algorithms, make use of generators of pseudorandom sequences of a certain length developed from primitive polynomials.
In this case, there are four sequence generators implemented with four shift registers with intermediate feedback signals of the type known as Gallois, with lengths of 17, 19, 21 and 23 stages respectively, that perform a variable number of shifts for each data clock cycle and from which a memory bit is obtained that is a logical combination of some of the bits of the shift registers mentioned and of the previous value of this memory bit.
The complete ciphering process is divided functionally into three stages:
Loading the keywords. A keyword of 128 bits has to be introduced through the input of the four shift registers which start from an initial state of all bistables set to zero, so that by the end of this process each register has a combination of ones and zeros determined by this keyword, and which is the state from which the algorithm independently starts to generate a pseudorandom data sequence that determines the ciphering of the input data. PA1 Pre-ciphering. In this stage the input to the registers has no effect but their content, obtained in the previous stage, is shifted a number of times during eleven data clock cycles; this number can be 2 or 3 depending on Boolean logic functions of certain determined bits of the four registers defined by the algorithm. When these 11 cycles have elapsed, a check is made to see if the content of the registers is zero, in which case the input bit of the corresponding register is set to one and the same process is repeated as has been described above for another 29 data clock cycles. Up to this point a series of prior operations have taken place in the shift registers, but the ciphering itself has not started. PA1 Ciphering. In this stage logic functions are performed with certain bits from the shift registers and with a memory bit which is the output bit of these logic operations in the preceding data clock period. The bit obtained as a result of these logic functions is combined in an exclusive-OR logic operation with the data that are to be encoded, so obtaining the data ciphered according to the DECT ciphering algorithm. PA1 R1.sub.n+p, R2.sub.n+p, R3.sub.n+p and R4.sub.n+p are the new values the registers would have after p clock cycles in the serial load mode, PA1 (T1).sup.p, (T2).sup.p, (T3).sup.p and (T4).sup.p are the transfer matrices corresponding to each generating polynomial but raised to the power p, and PA1 U1'.sub.n, U2'.sub.n, U3'.sub.3 are the input vectors formed by the same number of consecutive bits of the keyword as is the length of the corresponding register and shifted p bits by each clock cycle.
As prescribed by the algorithm, it is necessary to use 128 clock cycles of the sequence generator to load the keyword into the shift registers and 120 cycles more of the same clock to effect the pre-ciphering. The foregoing supposes that if the data clock is used as the sequence generator clock, a time equivalent to 248 data bits would be required to carry out the prior part before starting to generate ciphered output data.
Moreover, during the real ciphering stage, the need to perform 2 or 3 shift operations in the sequence generators to obtain a ciphered output bit which is combined with the input data bit and thereby achieve one ciphered data bit, implies the use of clocks working at frequencies 2 and 3 times greater than the data clock in order to maintain the timings correct during this ciphering process.
To reduce the times necessary to load the keyword and perform the pre-ciphering, it is common practice to make use of a higher frequency clock that permits both processes to be carried out in a shorter time whereby, the greater the frequency of this clock the shorter the time required to carry it out. However, the high frequencer clock causes, the current consumption to be greater. To reach a compromise between the two effects, a clock is normally used that is about ten times faster than the data clock and which shortens the aforementioned process times but does not produce an excessive increase in current consumption.
For the ciphering stage, as has already been mentioned, use is made of two clocks working at, respectively, 2 and 3 times the frequency of the data since, on some occasions, it will be necessary to shift a register twice per data bit period, and on others, three times.
As a consequence of this, not only the current consumption, which in the case of a DECT cordless terminal can be critical, is slightly increased but it also implies a need to have different clock signals which, in turn, must be generated from a single multiple frequency oscillator common to all of these clocks, in order to obtain the different clock frequencies by divisions of the output frequency from this oscillator.